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march 1998 1/20 th7426a/27a near infrared ingaas linear image sensor 300 pixels description these devices are based on a 300 ingaas photodiode li- near array, with a 26m pitch, using an in line pixel layout or a staggered pixel layout. two 150:1 ccd multiplexor chips, offering memory and de- layed readout capability, are hybridized on both sides of the photodiode array so as to build a complete module. specially designed to allow an accurate butting, those mo- dules could be tied together on request so as to provide an array extension with only one dead pixel at the splice. these devices are also available in a full cmos interface version : th74ka26a/th74ka27a or th74kb26a/th74kb27a. main features n near infrared spectral response: 0.8m to 1.7m n room temperature operation n low noise n high detectivity, wide dynamic range (>10 000) n high linearity, high modulation transfer function (mtf) n high output data rate : up to 6 mhz n intrinsic antiblooming n built in thermoelectric cooler and temperature sensor available n accurate mechanical indexes (ready to mount) selection guide reference pixel count layout pixel area pitch number of video outputs th7426a 299 in line 20x30m2 26m 2 th7427a 299 staggered 30x30m2 26m 2 th7428a 599 in line 20x30m2 26m 4 th7429a 599 staggered 30x30m2 26m 4 applications n suited for near infrared imaging n thermal imaging in the 200c to 800c range n high resolution multichannel spectrometry n fluorescence free raman spectrophotometry n on-line inspection and monitoring
geometrical characteristics element block diagram 2/20 th7426a/27a
absolute maximum ratings supply voltages (compare to vss, at any pin) 0 to +20v transient voltages (compare to vss, at any pin) 0 to +25v dc current (at any pin), 10ma except - thermoelectric cooler pins 6a except - temperature sensor +/-3ma operating temperature (temperature variation limited to 6c/min) -40 to +85c storage temperature (temperature variation limited to 6c/min) -40 to +85c electrostatic discharge sensitivity, mil-std-883 method 3015 device class 1 stresses above those listed under absolute maximum ratings may cause permanent devices failure. functionality at or above these limits is not implied. exposure to maximum ratings for extended periods may affect device reliability. to avoid any performance degradation,the device must be handled with grounded bracelet and stored in the conductive packing used for shipment. table 1 - electro-optical characteristics 15c internal operating temperature, 3ms integration time, typical voltage input (otherwise specified). parameter symbol th 7426 th 7427 unit remarks min. typ. max. min typ. max. dark voltage signal mean isolated pixels (photodiode dark current) v d (i d ) 3 0.6 100 4 0.8 120 mv mv pa see fig. 6 see note (1) noise in darkness (rms) mean isolated pixels s v d 200 1 200 1.2 v mv absolute photo response mean non uniformity non linearity over 1.5v range r prnu 10 1 +/-10 15 1 +/-10 vcm2/j % % see fig. 3-4-5 spectral response cut-off wavelength temperature shift l c d l c/dt 1.66 1.68 1.1 1.73 1.66 1.68 1.1 173 m nm/c at 50% r( l ) max modulation transfer function across array along array mtf 0.35 0.55 0.50 0.68 0.54 0.73 0.35 0.35 0.50 0.50 0.54 0.54 at 19.2 lp/mm see note (2) output saturation voltage vsat 2.5 2.5 v depends on preload level. see fig. 7 noise equivalent power at l =1.65 m m nep 0.35 40 6.7 0.35 40 4.4 fw fw nwcm -2 bw=1hz bw=167hz bw=167hz specific detectivity at l =1.65 m m d* 5.10 12 8.10 11 6.10 12 1.10 12 cmhz 1/2 w -1 cmhz 1/2 w -1 bw=1hz bw=167hz electron to voltage conversion factor quantum efficiency fc qe 0.26 0.8 0.26 0.8 v/e e/ph see fig. 5 image grade (number of blemishes) j k o e 1 5 10 na 1 5 10 na see note (3) electrical sample note : 1 already taken into account in mean v d (v d =idtifc ; ti=integration time ; q = 1.6 10 -19 c) q note : 2 maximum value is the theoretical value computed using the corresponding diode size note : 3 a pixel is considered as a blemish if : or - its dark voltage is higher than isolated pixel max value or - its noise is higher than isolated pixel noise max value or - its prnu is higher than +/- 10 % 3/20 th7426a/27a
table 2 - connection diagrams pin n even mo- dule # sym- bol designation pin n odd mo- dule # sym- bol designation 1...2 nc not connected 44...51 tc+ thermoelectric cooler (positive node) see notes (2) (3) 3...6 ts temperature sensor see note (3) 52...55 nc not connected 7...9 nc not connected 56 o vg1 lateral skimming gate bias 10 dnc do not connect see note (4) 57 o f x photodiode lateral transfer clock 11...14 nc not connected 58 o f pl electrical injection clock 15 e vdd output amplifier drain & re supplies 59 o vgl1 preload skimming gate bias 16 e vos video output signal (pixels 0-298) 60 o vgl2 preload storage gate bias 17 e gnd video ground 61 o f l2 shift register clock 2 (gated by re) 18 e vss ccd substrate bias (phases return) 62 o re read enable control signal (pixels 1-299) 19 e f r ccd reset clock 63 o f l1 shift register clock 1 20 e vdr reset bias 64 o vn photodiode substrate bias see note (1) 21 e vgs output gate bias 65 o vgs output gate bias 22 e vn photodiode substrate bias see note (1) 66 o vdr reset bias 23 e f l1 shift register clock 1 67 o f r ccd reset clock 24 e re read enable control signal (pixels 0-298) 68 o vss ccd substrate bias (phases return) 25 e f l2 shift register clock 2 (gated by re) 69 o gnd video ground 26 e vgl2 preload storage gate bias 70 o vos video output signal (pixels 1-299) 27 e vgl1 preload skimming gate bias 71 o vdd output amplifier drain & re supplies 28 e f pl electrical injection clock 72...75 nc not connected 29 e f x photodiode lateral transfer clock 76 dnc do not connect see note (4) 30 e vg1 lateral skimming gate bias 77...79 nc not connected 31...34 nc not connected 80...83 ts temperature sensor see note (3) 35...42 tc- thermoelectric cooler (negative node) see notes (2) (3) 84 nc not connected 43 nc not connected notes : 1 pin 22 and 64 are internally connected together notes : 2 in each group every pins must be connected and tied together in order to lower pin current density notes : 3 not connected on non cooled package notes : 4 dnc (do not connect). pins which are internally connected and must not be used. 4/20 th7426a/27a
pin description odd and even channels are fully independent, therefore same pin function will be found on odd and even sides. f pl this is the preload injection stage electrical input. each f pl pulse down overfills preload storage capacitance with electrons. f pl is connected to a diode cathode which anode is internally tied to vss. v gl1 this is the preload stage skimming gate. its bias determines the voltage up to which preload storage capacitance will be biased. thus it drives preload level. v gl2 this is the storage capacitance grid bias. it determines the bottom voltage of preload storing well, while v gl1 deter- mines its top level. preload capacitance thus is charged up proportionately to (v gl2 -v gl1 ) bias difference. f l1 this is the main register storage grid clock. charges are stored under f l1 when transfer is disabled (re at low le- vel). f l1 is also used for lateral transfers to input nodes. f l2 this is the main register transfer grid clock. f l2 is used to isolate f l1 content during lateral transfers. the main re- gister is beginning and ending with f l2 which therefore controls main register access and outputs. f l2 is gated by re input, it is internally pulled down when re is low, preventing transfers, preload injection, read out and isolating each f l1 well. re this is the read enable input. when high, it allows f l2 input connection to main register, when low, main register corresponding grids are pulled down whatever f l2 input level is. this input helps to serially read out two or more multiplexors with one single f l2 signal for all. data are stored into the main register as long as re is low, thus read out can occur later on. f x this is the lateral transfer grid command. lateral transfer is allowed when f x is at high level. f x is common to all input nodes, all photodiode information is collected at the same time. v g1 this is the lateral input stage skimming grid bias. this grid determines photodiodes reset bias, always the same from integration time to integration time. after photodiode reset (input node capacitance reset) extra charges leading to overcrossing v g1 level are skimmed back into f l1 main register wells. v n this is the ingaas photodiode common cathode bias. v n is available on odd and ev en side, however, both pins are connected together, to photodiode substrate. v gs this is main register output grid bias. it is used to isolate read out capacitance from main register. it allows charges to be read out when f l2 is at low level. v dr this is the read out capacitance reset bias. after each single read out, read out capacitance is cleared off (reset) to v dr level, during f r clock high state. 5/20 th7426a/27a
v dd this is the output amplifier power supply (high side). it also supplies the read enable switching device which ex- plains that i dd is different whether re is at high or low level. g nd this is the output amplifier low side power supply. g nd is linked to v ss through a diode, g nd being the cathode node. thus g nd must always be more positive than or equal to vss. it must be noticed that re switching device is powered from v dd to v ss .g nd is specific to output amplifier. v os this is the amplifier output. v ss this is the ccd multiplexor substrate bias. all applied biases and clock levels must be more positive or equal to v ss . t s these are the internal temperature sensor connections. temperature sensor is floating with respect to all other pin connections. pins 3 to 6 are internally connected together as well as pin 80 to 83. tc+ this is the internal thermoelectric cooler positive input (current enters) (all pins must be externally connected in or- der to lower current density into each pin). tc- this is the internal thermoelectric cooler negative input (current goes out). thermoelectric cooler connections are floating, with respect to all other pins. all pins must be externally connected in order to lower individual pin current density. it is advised to avoid pulsed current regulations to drive te cooler, since it may result in emc troubleshoo- ting inside component cavity. functional description individual ingaas diodes are reversed bias. the cathode node is common to all diodes and connected to a fixed potential vn. the anode of each diode is wire bonded to a lateral entrance of the readout ccd stage. these diodes behave as capacitors whose leakage current depends on dark current and illumination. this current tends to decrease the voltage across the capacitor. each diode capacity is first preloaded with a calibrated amount of negative char- ges (qb). after an integration time (ti), the amount of removed charges (qi) figures out the cumulated light absorption. so the measurement of the remaining charge amount (qs) in the diode capacitor gives access to qi (qi = qb - qs). this is called vidicon readout mode. ccd multiplexors fulfill all those operations. they provide preloading and readout functions for the separate odd and even pixel groups. the main ccd features consist in a two phase register ( f l1 and f l2 ) with longitudinal and lateral transfer ca- pability. following is a description of how those devices keep photodiodes under control and capture pixel signals. four main functions can be considered : - preload the potential gap between the two gates [v gl1 -v gl2 ] defines a potential well for preload calibration (qb), its filling and spilling occurs using an injection diode f pl . - main register charge handling at each individual transfer step, qs moves out of the 150th stage, while qb moves in the first stage. the longitudinal register stage requires a series of at least 150 steps to complete the preloading cycle. this transfer operation is inhi- bited if re (read enable) input is maintained at a low level. - photodiode information collection (and reset) the lateral input stage consists in 150 input diodes, each of them directly wire bonded to one photodiode, and con- trolled under a single common biasing gate v g1 and a lateral transfer gate f x . at the end of integration time (see timing diagram figure 1) : - the preload charges qb, stored in the register, are transferred simultaneously to the 150 photodiodes when f x is at high level and f l1 at low level, allowing the photodiode reset. - charges in excess (identified as qs) are collected back to the register by forcing f l1 at high level. at this step the register current information is the mirror image of the collected photo signal and, all photodiodes are reseted while a new ti starts. to isolate each stage from the other one, f l2 must be at low level during all lateral transfer operations. - data read-out at the end of the photodiode reset operation : - if re is forced to low level (timing diagram - figure 1), all qs information remain stored in the register and so, rea- dout is delayed .according to this situation a next photodiode reset procedure cant be operated until the full longitu- dinal transfer takes place (150 steps minimum). 6/20 th7426a/27a
- if re is activated or always at high level (timing diagram - figure 2), each stored charge is transferred to the rea- dout capacitance; this continuous readout mode is recommended for long integration time. qs conversion into voltage is supported by the readout stage capacitance, linked to a low output impedance ampli- fier. this capacitance is reset at v dr bias, before each pixel readout operation (high level f r ). due to the vidicon read out mode, qb level needs adjustment so as to provide enough carriers to sustain photocurrent and dark current during the integration time. pixel antiblooming is also resulting from vidicon mode since photodiodes cannot consume more electrons than qb. antismearing (frame to frame antiblooming) efficiency depends on the photodiode reset conditions, reverse bias recovering need a minimum qb condition such as : qb>clat .v d where : - clat is the individual lateral input node capacitance, clat ~1.5 pf (including photodiode, bonding pads...) where : -v d is the photodiode bias : v d =v n - 0.78v g1 - 8.7 7/20 th7426a/27a
multiplexor timing diagram * first even output data is always at preload level (multiplexor corresponding input is not connected see element block diagram) 8/20 th7426a/27a
table3-static characteristics symbol pin n even/odd function value unit note min typ max v dd 15/71 output amplifier 17.5 18 18.5 v (1) i dd with read enable disabled with read enable activated 0.7 1.1 ma ma (2) v dr 20/66 reset bias 15.3 15.5 16.5 v (1) v n 22/64 internally connected photodiode substrate bias 11 11.3 11.5 v g nd 17/69 video ground 0 2 v (3) v ss 18/68 register substrate v v g1 30/56 lateral skimming gate 1.9 2 2.1 v v gl1 27/59 preload skimming gate 2.8 3 5 v (4) v gl2 26/60 preload storage gate 3 4 5 v (4) v gs 21/65 register output gate 6.2 6.5 7 v note : 1 v dd -v dr >1.8v note : 2 for each v dd pin note : 3 recommendation: tied to v ss or, for best operation, hold at +0.5v above v ss note : 4 v gl1 and v gl2 are used to calibrate preloading level see fig. 7; to minimise noise effect, it is recommended notes : to get v gl1 and v gl2 from the same low noise supply. table4-d ynamic characteristics symbol pin n even/odd function value unit note min typ max f l1 low high 23/63 longitudinal transfer stage (120 pf typical) 0.1 9 0.3 9.5 0.7 10.5 v v f l2 low high 25/61 (120 pf typical if all re enabled) 0.1 9 0.3 9.5 0.7 10.5 v v f pl low high 28/58 preload injection diode (10 pf typ.) 5.8 9.5 6 12 6.7 12.5 v v f r low high 19/67 read out reset gate (10 pf typ.) 0.1 11.5 0.3 12 0.7 12.5 v v f x low high 29/57 lateral transfer stage (10 pf typ.) 0.1 7.8 0.3 8 0.7 8.2 v v re low high 24/62 read enable (15 pf typ.) 0.1 ( f l2 high +2,5v) 0.2 0.4 15 v v table 5 - miscellaneous data symbol pin n function value unit note min typ max i th 35 to 42 thermo cooler 3 6 a (5) 44 to 51 v os(dc) 16,7 video signal dc level (wrt vss) 12 v (7) z o output impedance 1.2 k w (7) rpt (at 0c) 3to6 80 to 83 temperature sensor resistance (recommended max. current 1 ma) 100 w (6) f p transfer frequency 0.5 3 mhz note : 5 see fig. 8a, 8b, 8c, 8d. note : 6 see fig. 9. note : 7 short circuit to gnd or vss exceeding 1 min duration may permanently damage the device 9/20 th7426a/27a
table 6 - timing and switching characteristics parameter symbol value unit note min. typ. max. integration time ti 0.05 3 ms clock period tck 0.33 2 s (3) read enable duration tre 149.5tck+t1 re +t2 re s rise time or fall time tr/tf 25 250 ns (4) delay t1re 0 120 ns set-up re t2re 150 850 ns lateral transfer duration t f x 522 s f x rise time or fall time tr/tf 25 150 ns (4) f 1 low level hold time tx1 1 1.7 s f 2 low level hold time tx2 4 20 s delay t f x 100 980 ns readout delay t f 1 100 200 ns longitudinal transfer f l1 rise time or fall time tr/tf 25 150 ns (4) f l2 rise time or fall time tr/tf 25 150 ns (4) preload duration t f pl 35 240 ns preload rise time or fall time tr/tf 25 50 ns (4) preload delay tpl 0 80 ns skimming time tsk 70 500 ns (1) readout diode reset duration t f r 35 240 ns (2) rise time or fall time tr/tf 25 120 ns (4) delay tr 0 10 ns (2) video signal set-up time t video 100 ns note : 1 better if no clock transition occurs during tsk time. note : 2 tr+t f r< f l2 high level duration. note : 3 duty cycle: 50% note : 4 rise time (tr) and fall time (tf) specified between 10% and 90% 10/20 th7426a/27a
electro-optical typical characteristics 11/20 th7426a/27a figure 3 : silicon window typical spectral response figure 4 : clear window typical spectral response figure 6 : dark voltage per 1ms integration time figure 6 : vs internal operating temperature figure 5 : clear window & silicon window quantum efficiency figure 7 : typical preload voltage vs v gl1 and v gl2 gate voltages
thermal characteristics (single stage te cooled package -subvariant n- only) tc<0 rpt = 100 {1+[3.90802 10 -3 t] - [0.580195 10 -6 t 2 ] - [4.7350 10 -12 (t-100) t 3 ]} tc>0 rpt = 100 {1+[3.90802 10 -3 t] - [0.580195 10 -6 t 2 ]} 12/20 th7426a/27a figure 8a : internal temperature vs figure 8a : thermo-electric cooler current figure 8b : internal to rear face temperature gap vs figure 8b : thermo-electric cooler current figure 8c : thermo-electric cooler voltage vs. figure 8c : thermo-electric cooler current figure 9 : pt resistance variation r = r(tc) - r(0c) vs. temperature figure 8d : rear face power dissipation vs. figure 8d : thermo-electric cooler current
outline drawing in the standard version devices are hermetically sealed in a jlead 84 like package with a near ir transparent window (see next drawing). the package basement includes a thermoelectric cooler and a temperature sensor, see figures 8-9 for ther- mal characteristics. silicon, with an antireflective coating is the window material. an optional version used an ar coated glass and an additional frame (numerical aperture f/3) to prevent parasitic lateral visible light. the photodiode array location is mechanically indexed upon the package rear face (opposite to the window) for fast accu- rate mounting. package variant (n) (thermoelectric cooler version) 13/20 th7426a/27a
ordering information th7426a v(1) w(2) a* b* c* g d* th7427a v(1) w(2) a* b* c* g d* (1) temperature range v = -40 to 85c (see c*) (2) package family ceramic jlead type a* image grade j, k, o, e see table 1 b* package variant s = standard silicon window r = clear glass window n = non sealed removable window c* package sub-variant (the detector temperature depends on the surrounding ambient and on device energy budget which is directly related to the built in thermo-cooler option efficiency.) - = without thermo-electric cooler; from -40 to +15c full performances(derated over) n = 1 stage thermo-electric cooler; from -40 to +60c full performances (derated over) p = 3 stages thermo-electric cooler; from -40 to +85c full performances d* quality level - = standard d/t = industrial level b/t = military levels s = space level 14/20 th7426a/27a
application information - preload generation preload is fed up when f pl is at low level. this process needs few time to be completed ( >35 ns). then skimming is nee- ded to calibrate qb. this step needs as much as possible time. therefore it is recommended to activate f pl as soon as f l2 is at low level, in order to spend most of f l2 low level duration for skimming. qb depends on (v gl2 -v gl1 ) difference, thus noise on qb may result from differential fluctuations between v gl1 and v gl2 .it is therefore recommended to get v gl1 and v gl2 biases on each side (odd or even) from the same power supply line. - preload level adjustment preload level must be chosen so as to covered both expected maximum signal and dark current resulting signal. it must be noti- ced that the vidicon mode implies output signal has the largest amplitude in darkness (since most of qb is to be readout). since output signal treatment difficulty may arise from its large amplitude it is better to reduce as much as possible its dyna- mic, thus to reduce preload level to the minimum required. from figure 6, dark voltage can be deduced, photosignal is computed from figure s3&4and application data (light flux, in- tegration time). preload must be 200 mv in excess to dark voltage and maximum photosignal sum. preload can be adjusted with (v gl2 -v gl1 ) biases, as indicated in figure 7, however it is recommended to act first on v gl2 . direct read out of pre- load level is possible in forcing f x at low level avoiding lateral transfer and photodiode read out. th7426a/27a maximum preload is about 2.5 v (corresponding to 10 7 electrons). - photodiode information collection as explained this operation needs two steps : a). qb injection into input nodes. b). skimming back into main register of extra charges. step a) needs at least 1 s to be completed (tx1). however, step b) is a longer process, which duration influences lateral transfer efficiency. it has been measured that 20 s is needed for less tha n1%tr ansfer non efficiency which raises to 2 % for 4 s skimming time (tx2). thus it is recommended to allow as long as possible skimming time, compatible with application requirement. - output signal format figures 1 and 2 give details on output signal. each reset ( f r ) pulse pulls up the output at reset level related to vdr bias. using typical biases, reset level reaches about 12 volts with respect to vss. notice that f r must be pulsed only when f l2 is at high level. just after reset pulse, output level is stabilizing to a steady level called floating diode level. this level is the very reset level to be taken into account for useful signal amplitude measurement. it is about 200 mv lower than reset level. then on f l2 falling edge, charges coming from main register last stage arrive. consequently, output signal drops down. the new steady level reached, counted from floating diode level represents the useful information - uos - uos amplitude is maximum when no lateral transfer has occurred, since it represents preload level. in darkness, after pho- todiode read out (lateral transfer) uos is reduced by dark voltage signal. under illumination uos is still smaller until satura- tion occurs (whole preload consumption), in this situation floating diode level is maintained until next pixel readout. - read enable operation re input simplifies device operation since it allows to use continuous f l2 clocks. however, one can force re at high level and generate external f l2 interruption during f x transfer. in this case, first pixel data will be read out at first falling edge of f l2 . after 150 f l2 periods all pixel data will have been read out, on 151 st f l2 period, output will be unused preload and so on until next f x cycle. when using re input, it must be noticed that re duration must at least allow 150 main register transfers ( f l2 periods) in order to guaranty that all main register stages contain a preload (qb) before next f x cycle. otherwise all photodiodes will not be properly reset at next f x cycle. when re is low, output signal is continuously at floating diode level, with f r transparencies. - interlacing odd even as odd and even sides are fully separated, it is possible to drive odd and even side with 180 phase shifted f l1 and f l2 ( f pl , f r with same phase with respect to their f l2 ), f x being identicals. in this manner odd output signals will be de- layed by half a tck period with respect to even outputs allowing, after common sampling, natural multiplexing and double pixel data rate. this opportunity is presented in application hints (figures 10 to 12). - mechanical mounting accurate mechanical references are provided in n and p subvariant packages (see ordering information and outline dra- wings). if optics are mechanically referred to these packages rear face, no tuning strategy could be implemented for scale manufacturing. 15/20 th7426a/27a
application hints figure 10 : application hint : device operation 16/20 th7426a/27a
figure 11 : application hint : signal treatment 17/20 th7426a/27a
figure 12 : timing diagramm for figure 10 &11 (output data : 1 mhz) 18/20 th7426a/27a
19/20 th7426a/27a note
20/20 th7426a/27a information furnished is believed to be accurate and reliable. however thomson-csf semiconducteurs specifiques assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of thomson-csf semiconducteurs specifiques. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. thomson-csf semiconducteurs specifiques products are not authorized for use as critical components in life support devices or systems without express written approval from thomson-csf semiconducteurs specifiques. 1998 thomson- csf semiconducteurs specifiques - printed in france - all rights reserved. this product is manufactured by thomson-csf semiconducteurs specifiques - 38521 saint-egreve / france. for further information please contact : thomson-csf semiconducteurs specifiques - route dpartementale 128 - b.p. 46 - 91401 orsay cedex / france - tl. : (33)(0) 1.69.33.00.00 / tlfax : (33)(0) 1.69.33.03.21. e-mail : lafrique@tcs.thomson.fr - internet : http://www.tcs.thomson-csf.com order code : dsth7426a/27at/0398 cr / ralis par graphic express - tl. : 01.46.55.27.24 - 10236 - 03/98

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